Flip-flops also must be designed to minimize clock power. To do this, clock gating is provided at two levels in the clock tree, as well as for each individual flip-flop, to avoid wasting power on unused branches. This can reduce clock power to less than half that of alternative 28-nm FPGAs, averaged over a suite of designs (as shown in Figure 3, which uses the PolarFire FPGA as an example of the new fabric approach).
The choice of operating voltage is also important. A power-performance trade-off must be carefully optimized for a 1.0-V core logic supply. In the case of FPGAs fabricated with SONOS NV technology on a 28-nm node, this is somewhat less than the 1.05-V nominal voltage for the process on which it’s manufactured. Customers desiring extra speed still have the option to use the full 1.05 V supply.